RetroArch
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#include <gctypes.h>
Go to the source code of this file.
Macros | |
#define | LC_BASEPREFIX 0xe000 |
#define | LC_BASE (LC_BASEPREFIX<<16) |
#define | LCGetBase() ((void*)LC_BASE) |
Functions | |
void | DCEnable () |
Enable L1 d-cache. More... | |
void | DCDisable () |
Disable L1 d-cache. More... | |
void | DCFreeze () |
Current contents of the L1 d-cache are locked down and will not be cast out. More... | |
void | DCUnfreeze () |
Undoes actions of DCFreeze(). More... | |
void | DCFlashInvalidate () |
Invalidate L1 d-cache. More... | |
void | DCInvalidateRange (void *startaddress, u32 len) |
Invalidates a given range of the d-cache. More... | |
void | DCFlushRange (void *startaddress, u32 len) |
Flushes a given range. More... | |
void | DCStoreRange (void *startaddress, u32 len) |
Ensures a range of memory is updated with any modified data in the cache. More... | |
void | DCFlushRangeNoSync (void *startaddress, u32 len) |
Flushes a given range. More... | |
void | DCStoreRangeNoSync (void *startaddress, u32 len) |
Ensures a range of memory is updated with any modified data in the cache. More... | |
void | DCZeroRange (void *startaddress, u32 len) |
Loads a range of memory into cache and zeroes all the cache lines. More... | |
void | DCTouchRange (void *startaddress, u32 len) |
Loads a range of memory into cache. More... | |
void | ICSync () |
Performs an instruction cache synchronization. More... | |
void | ICFlashInvalidate () |
Invalidate the L1 i-cache. More... | |
void | ICEnable () |
Enable L1 i-cache. More... | |
void | ICDisable () |
Disable L1 i-cache. More... | |
void | ICFreeze () |
Current contents of the L1 i-cache are locked down and will not be cast out. More... | |
void | ICUnfreeze () |
Undoes actions of ICFreeze(). More... | |
void | ICBlockInvalidate (void *startaddress) |
Invalidates a block in the i-cache. More... | |
void | ICInvalidateRange (void *startaddress, u32 len) |
Invalidate a range in the L1 i-cache. More... | |
void | LCEnable () |
void | LCDisable () |
void | LCLoadBlocks (void *, void *, u32) |
void | LCStoreBlocks (void *, void *, u32) |
u32 | LCLoadData (void *, void *, u32) |
u32 | LCStoreData (void *, void *, u32) |
u32 | LCQueueLength () |
u32 | LCQueueWait (u32) |
void | LCFlushQueue () |
void | LCAlloc (void *, u32) |
void | LCAllocNoInvalidate (void *, u32) |
void | LCAllocOneTag (BOOL, void *) |
void | LCAllocTags (BOOL, void *, u32) |
#define LC_BASE (LC_BASEPREFIX<<16) |
#define LC_BASEPREFIX 0xe000 |
void DCDisable | ( | ) |
Disable L1 d-cache.
void DCEnable | ( | ) |
Enable L1 d-cache.
void DCFlashInvalidate | ( | ) |
Invalidate L1 d-cache.
An invalidate operation is issued that marks the state of each data cache block as invalid without writing back modified cache blocks to memory.<br> Cache access is blocked during this time.Bus accesses to the cache are signaled as a miss during invalidate-all operations.
Flushes a given range.
If any part of the range hits in the d-cache the corresponding block will be flushed to main memory and invalidated.<br> <b><i>NOTE:</i></b> This function invokes a "sync" after flushing the range. This means the function will stall until the CPU knows that the data has been writen to main memory
[in] | startaddress | pointer to the startaddress of the memory range to flush. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of range to be flushed. NOTE: Should be a multiple of 32 |
Flushes a given range.
If any part of the range hits in the d-cache the corresponding block will be flushed to main memory and invalidated.<br> <b><i>NOTE:</i></b> This routine does not perform a "sync" to ensure that the range has been flushed to memory. That is, the cache blocks are sent to the bus interface unit for storage to main memory, but by the time this function returns, you are not guaranteed that the blocks have been written to memory.
[in] | startaddress | pointer to the startaddress of the memory range to flush. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of range to be flushed. NOTE: Should be a multiple of 32 |
void DCFreeze | ( | ) |
Current contents of the L1 d-cache are locked down and will not be cast out.
Hits are still serviced, but misses go straight to L2 or 60x bus. Most cache operations, such as DCFlushRange(), will still execute regardless of whether the cache is frozen.<br> <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache. We use the word "freeze" to distinguish it from the locked cache and DMA features.
Invalidates a given range of the d-cache.
If any part of the range hits in the d-cache, the corresponding block will be invalidated.
[in] | startaddress | pointer to the startaddress of the memory range to invalidate. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of the range to invalidate. NOTE: Should be a multiple of 32 |
Ensures a range of memory is updated with any modified data in the cache.
<b><i>NOTE:</i></b> This function invokes a "sync" after storing the range. This means the function will stall until the CPU knows that the data has been writen to main memory
[in] | startaddress | pointer to the startaddress of the memory range to store. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of the range to store. NOTE: Should be a multiple of 32 |
Ensures a range of memory is updated with any modified data in the cache.
<b><i>NOTE:</i></b> This routine does not perform a "sync" to ensure that the range has been flushed to memory. That is, the cache blocks are sent to the bus interface unit for storage to main memory, but by the time this function returns, you are not guaranteed that the blocks have been written to memory
[in] | startaddress | pointer to the startaddress of the memory range to store. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of the range to store. NOTE: Should be a multiple of 32 |
Loads a range of memory into cache.
[in] | startaddress | pointer to the startaddress of the memory range to load. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of the range to load. NOTE: Should be a multiple of 32 |
void DCUnfreeze | ( | ) |
Undoes actions of DCFreeze().
Old cache blocks will now be cast out on subsequent L1 misses.<br> <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache. We use the word "freeze" to distinguish it from the locked cache and DMA features.
Loads a range of memory into cache and zeroes all the cache lines.
[in] | startaddress | pointer to the startaddress of the memory range to load/zero. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of the range to load/zero. NOTE: Should be a multiple of 32 |
Invalidates a block in the i-cache.
If the block hits in the i-cache, the corresponding block will be invalidated.
[in] | startaddress | pointer to the startaddress of the memory block to invalidate. NOTE: Has to be aligned on a 32byte boundery |
void ICDisable | ( | ) |
Disable L1 i-cache.
void ICEnable | ( | ) |
Enable L1 i-cache.
void ICFlashInvalidate | ( | ) |
Invalidate the L1 i-cache.
An invalidate operation is issued that marks the state of each instruction cache block as invalid without writing back modified cache blocks to memory.<br> Cache access is blocked during this time. Bus accesses to the cache are signaled as a miss during invalidate-all operations.
void ICFreeze | ( | ) |
Current contents of the L1 i-cache are locked down and will not be cast out.
Hits are still serviced, but misses go straight to L2 or 60x bus.<br> <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache. We use the word "freeze" to distinguish it from the locked cache and DMA features.
Invalidate a range in the L1 i-cache.
If any part of the range hits in the i-cache, the corresponding block will be invalidated.
[in] | startaddress | pointer to the startaddress of the memory range to invalidate. NOTE: Has to be aligned on a 32byte boundery |
[in] | len | length of the range to invalidate. NOTE: Should be a multiple of 32 |
void ICSync | ( | ) |
Performs an instruction cache synchronization.
This ensures that all instructions preceding this instruction have completed before this instruction completes.
void ICUnfreeze | ( | ) |
Undoes actions of ICFreeze().
Old cache blocks will now be cast out on subsequent L1 misses.<br> <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache. We use the word "freeze" to distinguish it from the locked cache and DMA features.
void LCDisable | ( | ) |
void LCEnable | ( | ) |
void LCFlushQueue | ( | ) |
u32 LCQueueLength | ( | ) |